1. Field
Embodiments of the invention relate generally to the field of chip level interconnections for integrated circuits, and more specifically to making chip level interconnections using carbon based dielectric and carbon nanotube wires.
2. Background
An integrated circuit requires interconnections between the various devices that are constructed in the silicon wafer. The interconnections can limit the maximum data rate that is possible to achieve within the integrated circuit. Copper is presently used for integrated circuit interconnection wires or traces. Dielectrics like silicon dioxide or doped silicon dioxide are used to insulate the copper traces. Together the resistance (R) of the copper trace, used for the interconnection, and the capacitance (C) that exists across silicon dioxide contained between copper traces, forms a time constant (RC), which introduces a time delay that limits the maximum rate at which data can be transferred to and from the devices within the integrated circuit. The capacitance that exists across the insulation material is related to the dielectric constant of the silicon dioxide. Consequently, a lower dielectric constant results in a lower capacitance across the dielectric and a higher data transfer rate to and from the devices within the integrated circuit.
Copper is diffusive, possessing inherent electrical resistance that limits the minimum achievable time constant previously described. Similarly, present insulation materials like doped silicon dioxide have dielectric constants that cannot be reduced much further than present values. Fluorine is used to dope silicon dioxide, thereby reducing its dielectric constant from approximately 4 to 3.0-4.0. There is no other metal that can exceed the electrical conductivity of copper, at device operating temperatures, and fluorine doped silicon dioxide is limited in terms of how much further its dielectric constant can be reduced. Therefore, the current data transfer rates of an integrated circuit can be limited by the electrical properties of the interconnections made between devices within the integrated circuit.
Device size within an integrated circuit presents another limitation to data transfer speeds. The data transfer speed, density, and efficiency of microelectronic devices all rise rapidly as the minimum device size decreases. Present interconnections using copper traces and doped silicon dioxide present limitations to shrinking the device size much below present geometries.